Aerospace integrated circuits are the core foundation technology of aerospace engineering,and their long-term sustained development is crucial for China's progress towards becoming a space power.This article introduces the development status of international integrated circuits,the development trends of aerospace integrated circuits,the development strategies of United States and Europe regarding aerospace integrated circuits,as well as the current development situation of China's aerospace integrated circuits.It elaborates on several considerations for the development of China's aerospace integrated circuits.

Chiplet integrates multiple small chips into a system chip,aiming to achieve various goals such as chip reusability,heterogeneous integration,performance enhancement,and cost reduction.The development trends of the Chiplet primarily encompass heterogeneous integration,innovative interconnects,and advanced packaging.Notably,interface interconnection is the key of Chiplet technology.Interconnection using the design of physical layer interfaces and data transmission protocols,considering factors like process,packaging techniques,power constraints,and requirements of upper-level applications.Serial and parallel interconnects are two choices for chip-to-chip physical layer interfaces,each with its own advantages and application scenarios.Additionally,for different propagation media,emerging interconnect technologies such as optical and wireless interconnects offer higher bandwidth,lower power consumption,and more flexible interconnection topologies.Chiplet is promising to bring significant breakthroughs and advancements to the field of electronics,promoting more efficient,flexible,and innovative chip design and manufacturing.

An investigation on radiation-hardened technology of single event effect(SEE)for power MOSFETs is described in the paper.In order to decrease the gain of the parasitic bipolar junction transistor (BJT),an optimized reversed-body implant process is utilized.Meanwhile,a variable-doping buffer of epitaxy is designed to reduce the gradient of vertical electric-field,leading to a decreased accumulation of carriers nearly the sensitive gate area.Results show under rated Vds and 15 V negative Vgs bias,the single event burnout (SEB) and single event gate rupture (SEGR) LET of radiation-hardened MOSFETs is above 75 MeV·cm²/mg.Under the same radiation condition,the negative gate-source bias of radiation-hardened MOSFETs reaches to 15~17 V.There is an obvious increase comparing to the unhardened MOSFETs of 7~10 V.

Transient circuit simulations often necessitate the construction of linear system models,where the sequential solution of triangular matrices with multiple right-hand terms becomes a time-intensive process.To expedite the computational efficiency of back-substitution for these matrices in transient circuit simulations,this paper proposes a parallel computing method based on a heterogeneous platform.The method prioritizes the computation of multiplications relevant to the solution vector,exploiting the inherent parallelism of back-substitution calculations.The architecture features a core operation array with multiple floating-point calculation units and a control module employing a two-tiered master-slave state machine.Using the Zynq UltraScale series FPGA,specifically the XCZU15EG model,our architecture is compared to an Intel 24-core CPU platform utilizing the MKL solving library in linear matrix resolution experiments.The matrices used exhibit characteristics of being symmetric positive definite,diagonally dominant,and dense with a sparsity exceeding 50%.The proposed acceleration architecture achieves an average speedup factor of 22,with solution errors falling within the range of 10^-17 to 10^-14.The experiment results demonstrate the architecture's significant enhancement of matrix solution speed,especially suitable for forward and backward substitution resolution of high-dimensional linear matrices in transient circuit simulations.

To evaluate the single event effects vulnerability of electronic systems being used in space environment,and verify the effectiveness of system-level hardening methods against radiation,this article conducts relevant research on system level single event effect testing methods.Feasibility of irradiating devices in electronic systems one by one under laboratory environment to evaluate single event functional interrupt rate is confirmed.It is suggested that many methods could be used to get the vulnerability data of devices.The procedure to directly sum up the cross section value corresponding to each device is pointed out to be not reasonable.Through all the above suggestions,it is able to support the test for system-level single event effects.

Silicon-based optoelectronic technology combines the advantages of high integration of large-scale IC manufacturing technology with the advantages of large bandwidth,high speed ability of optoelectronic chips,and promotes the wide application of silicon-based optoelectronic devices in high energy physics experiments,medical imaging and high energy particle colliders.However,photodetectors used in space environment and medical detectors are expected to be subjected to a cumulative fluences of ~10¹² particles/cm² during their operating cycle,while detectors used in large particle colliders are expected to a radiation fluences of ~10¹⁴ particles/cm².In this paper,the advance in space radiation effects of Si-based photodetectors is described in detail,including the radiation effects of Si-based photodiodes,avalanche photodiodes,single photon detectors and photomultiplier after irradiation by different particles.The research results show that the hardness of total ionizing dose for the detector is good,and the displacement damage is the main reason for the degradation of detectors’ key parameters.Due to the difference in working principle,all kinds of devices show different degradation behavior and degradation mechanism in the space radiation.

High-speed extra short reach (XSR) wireline interfaces are an important technical solution for chiplets interconnection.The traditional continuous time linear equalizer (CTLE) based on current mode logic (CML) has gradually failed to meet the demand for high-density,miniaturization,and low-power consumption of chiplet data interfaces due to the use of high supply voltage and passive components.To address this problem,this paper proposes an inverter-based CTLE with mid-frequency compensation (MFC) to transmit 28 Gb/s non-return to zero (NRZ) signals as well as 56 Gb/s 4-level pulse amplitude modulation (PAM4) signals in XSR applications.The design is implemented in a 28 nm CMOS process with a core area of only 400 μm².After an XSR channel at -9.4 dB@14 GHz,the post-layout simulation results show that the proposed CTLE improves the eye width of the 28 Gbaud NRZ and PAM4 signals by 0.14 UI and 0.41 UI,and the eye heights by 328 mV and 119 mV,respectively.The power consumption is 6.12 mW at 56 Gb/s PAM4 signaling.

As the size of semiconductor technology gradually approaches the physical limit,the progress of process technology has led to a decreasing improvement in the power consumption,area,and other performance of chips,semiconductor technology has entered the “post-Moore era”.In order to further meet the high bandwidth communication needs brought about by the rapid development of machine learning,artificial intelligence,and other information and communication industries,Chiplet technology which based on advanced interconnection and packaging techniques,steps into the picture.Chiplet technology disassembles the original complex multifunctional SoC chip into small chips with small area,low cost,and different process nodes,and assembles them through advanced packaging technology,which has received high attention from academia and industry due to its advantages of high yield,low cost,high integration,strong performance,good flexibility,and fast time-to-market.This paper summarizes and elaborates on the technical characteristics,advantages,development history,and specific applications of Chiplet.Meanwhile,the core technologies of Chiplet,especially Chiplet D2D interconnect technology,are introduced in detail.Finally,the existing technical issues and challenges of Chiplet are described,and the suggestions for future development are put forward.

In high-speed wireline communication,clock-forwarding receivers requires the de-skew circuit to achieve the optimal sampling relationship between the clock and the data,and to ensure the synchronization of multiple data channels.A global de-skew scheme is proposed in the paper,which only uses one data and clock channel for alignment,and implements multi-channel data synchronization by clock delay matching and distribution techniques,reducing the power and area overhead by the independent de-skew circuit for each channel.The proposed receiver consists of 8 data channels,1 half-rate forwarded clock channel,and a global de-skew circuit based on the delay-locked loop.Based on 180 nm CMOS technology,at a data rate of 2.5 Gb/s,it can remove any skew between the input clock and data,and obtain the sampling phase at the center of the data eye,with the ability of clock duty cycle calibration.At a supply voltage of 1.8 V,the total power consumption of the proposed receiver is 187 mW,occupying the area of 0.16 mm²,saving 45.2% and 62.8% of power and area overhead,respectively,compared with the independent de-skew scheme for each channel.

To solve the problems of poor route ability in flexible printed circuit board,a bus planning algorithm based on pattern routing is proposed,which approximates detailed routing and reduces the precision error between detail routing and bus planning.At the same time,four routing patterns and several fan-out strategies are designed according to manual experience to simulate the possible situation of resource allocation in pin area and arrangement combination of pin areas.Besides,a layer assignment algorithm is designed to comprehensively evaluate the current routing results and the future impact on other nets.According to the restriction that vias are not allowed in the channel,the non-intersecting sequence of the routing topology of the nets in the channel is obtained according to the position sequence of pin areas connected with the channel,which is used as the constraint of the arrangement sequence of the points on the boundary line.Finally,the results in each pattern are comprehensively compared,and the least expensive result is selected as the final bus planning result. Experimental results on industrial cases show that the proposed algorithm realize better performance compared with the existing flexible printed circuit board bus planning algorithm.

A single-event burnout (SEB) hardened design based on N-type lateral double-diffused metal-oxide-silicon (NLDMOS) devices with a Nbuffer layer is proposed in this paper.The electrical and single-event characteristics of NLDMOS is verified by TCAD simulation.Without changing the device performance,the 18 V NLDMOS SEB trigger voltage increases from 22 V to 32 V,reaching the theoretical maximum,which is the avalanche breakdown voltage of the device.The NLDMOS device with an Nbuffer structure can suppress the peak electric field transfer when the parasitic bipolar transistor is turned on due to single paricle incident,and avoid avalanche breakdown of the device causing SEB.Furthermore,Nbuffer is also suitable for SEB hardening of 18~60 V NLDMOS.

Facing the challenge of the "area wall" in chip design,there is a significant increase in chip manufacturing costs.The chiplet technology enables the production of small area chips using a mature process,and composing by advanced packaging techniques,which can overcome the limitations imposed by the area wall,facilitating agile chip design and reducing overall design costs.Determining an optimal chiplet particle size to meet flexible chip design requirements remains a crucial issue when utilizing chiplet technology.Furthermore,achieving interconnectivity between functional chiplets after dividing chip functions is pivotal for realizing the final functionality of the chip.Therefore,this paper provides a comprehensive review of recent research on chiplet function division,spatial exploration in chiplet design and the influence of chiplet function division on the inter-chip interconnect,while also pointing out that chipet design methodology is an important research direction for the development of chiplet technology in the future.

With the development of integrated circuits to the Beyond Moor era,the heterogeneous integration technology has become an emerging direction of microelectronics.The interconnect interface,the key to the heterogeneous integration technology, is critical to heterogeneous integrated chip and system.In order to promote the implementation of heterogeneous integrated interconnect interface, the structure of the heterogeneous integrated chip and system is described and the heterogeneous integration technology is summarized into four technical routes:large chip by integrated chiplets, larger chip by integrated large chips,wafer-level chips and wafer-level systems. The characteristics of the heterogeneous integrated interconnect interface are summarized.The current research status and existing problems in the industry and academia around the heterogeneous integrated interconnect interface are analyzed.Finally,the future development trend and the needed technical characteristics of the heterogeneous integrated interconnect interface are given by this article.

As novel non-volatile memory,magneto-resistive random access memory (MRAM) has broad application prospects in the field of embedded memory due to its excellent read and write speed and endurance characteristics.However,since the customized design of MRAM usually takes several months to complete,it requires a long design period,which conflicts with the need for a faster design iteration of the system-on-chip.As a tool for quickly generating memory designs,the memory compiler is an effective means to resolve this contradiction.This article starts with the fully customized design process of magnetic random access memory and conducts a survey on the research status of various types of memory compilers.We summarize the current status and challenges of memory compiler design from published work and finally discuss the design methodology of magnetic random access memory compiler.

Currently,analytical methods have achieved the best results for VLSI floorplanning.Module flipping has real applications and can further optimize floorplanning results,but analytical methods cannot handle modules flipping in floorplaning.Therefore,this paper attempts to solve this problem by using a unified analytical method,and proposes a new force,i.e.,the flipping force,for modules flipping.The flipping force can guide each module's flipping to its desired direction based on wire length optimization during the global floorplanning stage.In addition,based on the electrostatic field model,this paper designs a new global floorplanning flow in which special treatment is applied to the density calculation of large-size modules.The aim is to reduce the repulsion of these modules and allow other modules to be placed closer to them,thus achieving a more uniform distribution of modules.To better utilize the whitespace between the floorplan boundary and large modules,a gap handling method is proposed.Finally,a post-floorplanning stage is applied to further optimize the floorplanning result.This stage involves re-optimizing the modules flipping directions using a mixed-integer linear programming,followed by applying our proposed new whitespace redistribution method.The whitespace redistribution method reduces the number of constraints in the linear programming problem and allows multiple rounds of optimization,leading to a more effective reduction of wire length compared to previous methods.The experimental results on HB+ and ami49_x benchmark circuits show that the proposed floorplanning algorithm achieves an average half-perimeter wire length reduction of at least 13.3% and 13.7%,respectively,compared to state-of-the-art floorplanning algorithms.

Given the current usage status of natural gas flow computer software in China,there is an urgent need for a versatile and highly powerful flow computer system software.This article investigates the advantages and disadvantages of existing traffic computer system software in the market,and develops a universal traffic computer system software using programming software such as MySQL database and Visual Studio.At the same time,the practicality of the software is verified.The software adopts a menu framework structure,fully considering the requirements of on-site traffic computer operators.The system operation is simple and convenient,the functions are complete,and the page data is concise and easy to understand.