Three-dimensional (3D) imaging technology based on Time-of-Flight (ToF) belongs to active 3D imaging technology.It calculates the distance information of the target object by measuring the time needed for modulated light to "fly" back and forth between the target object and the sensor.Compared to other 3D imaging methods, ToF-based 3D imaging methods have significant advantages such as miniaturization, simple structure,and low power consumption.With the development of technology,Indirect Time-of-Flight (IToF) image sensor pixel size gradually decreases,resolution increases,and accuracy improves,making it applicable in various scenarios.However,it still faces challenges such as background light interference,multipath interference,and motion artifacts.The working principle of ToF image sensors is introduced in section 1.The parameter indicators of ToF image sensors and their development trends are analyzed in section 2.The challenges faced by ToF image sensors are analyzed and the solutions are proposed in section 3.The image correction and restoration algorithms applied to ToF technology are introduced in section 4.
Single-photon imaging technology involves multiple aspects such as semiconductor processes,optoelectronic devices,and integrated circuit design.Based on single-photon avalanche diodes,single-photon imaging technology offers high dynamic two-dimensional grayscale imaging,high-precision three-dimensional imaging,and fluorescence lifetime imaging capabilities.It has significant application prospects in fields such as security surveillance,autonomous driving,and biomedicine.With the rapid development of semiconductor process technology,single-photon imaging technology is expected to become a widely used next-generation visual perception technology.This article provides a systematic introduction to imaging technology based on single-photon avalanche diodes,including the device structure of single-photon avalanche diodes,key circuits involved in single-photon imaging,and the latest research progress in gray scale and temporal resolution single-photon image sensors.
Image sensors,as crucial devices for capturing visual information,convert perceived light signals into electrical outputs.Currently,the manufacturing technology for image sensors based on complementary metal-oxide-semiconductor is quite mature.However,there is still a demand for miniaturized and multifunctional image sensors in certain specific application scenarios.Facing this challenge,image sensors based on two-dimensional (2D) semiconductors,with their rich material systems and excellent photoelectric properties,demonstrate potential in miniaturization and high integration,offering new opportunities for the development of the image sensor field.This paper first discusses the bandgap characteristics of 2D semiconductors and their corresponding spectral response ranges,showcasing single-pixel imaging technology based on 2D semiconductors.It then describes how the in-plane anisotropic properties of atomic arrangements in 2D semiconductors are utilized to successfully construct polarization-sensitive image sensors.Finally,it explores how the ongoing maturation of large-area growth technologies for 2D semiconductor materials can further facilitate the construction of image sensor arrays based on 2D semiconductors.
Terahertz wave is an electromagnetic wave between millimeter wave and infrared light,which has many feature like strong penetration capability,non-ionization and high instantaneous bandwidth.For these qualities,terahertz waves have a wide range of potential applications in non-destructive testing,medical imaging,safety inspection,and other areas.In the imaging system,the detector is an essential part.This paper presents a structure that combines the output of narrow-band detectors with different center frequencies to realize wide-band detection.In order to reduce the area,these narrowband detectors adopt a nested structure,which means that the high-frequency narrowband detectors are placed inside the low-frequency narrowband detectors in turn.Each narrow-band detector includes a loop antenna,a matching network and a field effect transistor (FET) detector circuit.The detector is fabricated in a 65 nm standard CMOS process,and the detection frequency range covers 100 GHz to 1 000 GHz.Based on this broadband detector,we propose a terahertz focal plane imaging system,which mainly consists of a terahertz radiation source,a PTFE lens,a broadband CMOS detector,etc.The measurement results have shown that the focal plane imaging system is capable of stably imaging at frequencies of 100 GHz,220 GHz and 300 GHz.The imaging quality improves significantly with increasing frequency.In order to solve the problem of missing information in measurement images,the morphological closing algorithm is used to process the original image.This algorithm effectively fills in the missing information and enhances the quality of the image.
Aiming at the requirement of high-speed and high linearity of CMOS image sensor for high-speed application devices,this paper realizes a Latch-ADC applied to image sensor on the basis of traditional SS ADC (Single-Slope ADC,Single-Slope analog-to-digital converter),with an operating frequency of 600 MHz.Latch-ADC can use multi-column pixels to share a Gray Code Counter,and quickly lock and store data through Latch structure,which realizes the functions of counter and SRAM in SS ADC.In this paper,a high-speed 12bit Latch-ADC is implemented by using 110 nm technology.Through simulation verification,the Latch-ADC in this paper has high linearity,with each conversion period of 7.094 μs,average power of 180.3 μW,and conversion power consumption of 1.279 nJ.
Aiming at the application requirements of high frame rate CMOS image sensors,a hybrid analog-to-digital converter (ADC) combining successive approximation register (SAR) and single slope (SS) structures is proposed.The resolution of this ADC is 12-bit,with SAR ADC achieving high 6-bit quantization and SS ADC achieving low 6-bit quantization.The ADC adopts a fully differential structure to eliminate fixed misalignment of the sampling switch and reduce nonlinear errors.At the same time,asynchronous logic circuits are used in SAR ADC to further shorten the conversion cycle.The circuit is designed and implemented using 110 nm 1P4M CMOS technology.The post-layout simulation results show that at clock frequency of 20 MHz,the conversion period is only 3.3 μs,the spurious free dynamic range is 77.12 dB,the signal-to-noise distortion ratio is 67.38 dB,and the effective bit is 10.90 bits.
In response to issues such as abnormal degradation of chip performance caused by electromagnetic pulses in power application scenarios,and unclear failure mechanisms of devices such as MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistors) within the chip,TLP (Transmission Line Pulse) pulses,with amplitude and width of 8 V and 100 ns,are applied into gate oxide layer of 5 V NMOS devices.The output characteristic curves Id-Vd and the transfer characteristic curves Id-Vg under different pulse cycles are measured.By calculating the device transconductance under different TLP number,the threshold voltage VT and carrier mobility with TLP pulse are obtained.The test results show that under the same drain voltage Vd and gate voltage Vg, the drain current Id of the device increases with the increase of the number of TLP pulses.TLP pulses cause a significant decrease of VT,which decreases by about 25.66% under 20 000 TLP pulses,TLP pulses caused the VT of the device to increase exponentially,and the fitting index is between 0.11~0.15.The influence of TLP pulses on the carrier mobility in the channel is not obvious.
This paper designs and realizes a data communication interface between the host and ARM based on FPGA is designed and implemented.The PCIe interface function for interacting with the host and the FMC interface function for interacting with ARM are implemented by FPGA.The transmission performance testing of PCIe and FMC interfaces,as well as the data loop testing between the host and ARM had been completed.The test results show that the overall system design requirements have been achieved,with the PCIe 1.0 interface speed reaching 820 MB/s.
Aiming at the problems of low transmission volume and slow speed of distribution automation communication in the process of transportation electricity,cloud edge collaboration mode and device to device (D2D) module are introduced to improve the communication structure between distribution automation equipment based on the industrial 4G Beidou distribution automation communication technology.Firstly,the relay communication network is built with the base station to improve the data transmission speed in the distribution network.Then,the security device manager (SDM) algorithm is improved,and the blocking characteristics of the channel are calculated by obtaining the bit error rate of each transmission channel.Finally,the blocking channel is modulated to make the transmission data more cooperative and further improve the transmission speed.The test results show that the maximum amount of communication detected by this system is 48 TB,and the average transmission speed is 10 MB/s,which indicates that this system has high applicability.
In current aerospace missions,the SRAM-based FPGA is susceptible to single-event effects,resulting in unexpected functional failures.In order to mitigate the impact of single-event effects and reduce the workload of repetitive design and testing,a bus-based FPGA program upload-scrubbing ASIC is designed.The ASIC supports multiple buses,adapts to various FPGAs,and is compatible with different memory types.It is utilized for tasks such as FPGA program loading,scrubbing,program upload,and other on-orbit maintenance operations.Firstly,the ASIC's system-level design,module-level design,and workflow planning are presented.The principle of ASIC resistance to single-event effects is briefly described.By designing compatible communication protocols,the ASIC simultaneously supports CAN bus and RS485 bus.By analyzing the FPGA configuration bitstream structure,the ASIC supports loading and scrubbing 9 types of FPGAs and achieves domestic compatibility.By converting the data format of memory,the ASIC can store the configuration bitstream in various memories,including BPI Flash,SPI Flash,PROM,and others.The triggering of scrubbing,SEFI detection,and execution of scrubbing are discussed.Analyzing and simulating the factors affecting the upload speed of the ASIC.Utilize prototype verification board,ASIC verification board,and pluggable FPGAs and memory floating small boards to complete various functional verifications before and after tape-out.The verification results are as expected.The effectiveness of the scrubbing is evaluated and compared with other on-orbit maintenance schemes.The bus-based program upload-scrubbing ASIC has certain advantages and can efficiently and reliably meet the various on-orbit maintenance requirements of aerospace FPGA.
In view of the difficulty in collecting panoramic information of power grid transmission lines and the inaccuracy of point cloud information processing,a three-dimensional airborne radar point cloud information acquisition system for power grid panoramic transmission lines is proposed.The system realizes the design and selection of airborne radar hardware through the design of airborne radar signal processing system and the selection of acquisition equipment.It uses LiDAR combined with Inertial Measurement Unit to accurately collect point cloud data of transmission lines.Using the combination of color information and intensity information in point cloud data,the point cloud data is classified and processed to realize the processing of point cloud data information.The experiment results show that the acquisition error of the system is smaller than that of LiDAR only,and the maximum error is 0.21,and the minimum error is 0.08.The classification accuracy of the system for different objects is different,and the classification accuracy of the transmission line can reach 97%,which is higher than the traditional method and the single point cloud data processing and classification method based on intensity information.
Based on the existing ZYNQ+FPGA ADC universal testing platform of the 58th China Electronics Technology Group Corporation,this paper carries out a detailed dynamic index test for the six-channel analog-to-digital conversion device AD73360.Data processing and analysis are realized by invoking MATLAB in LabVIEW of upper computer.As a result of the acquisition control and processing system has been designed,the design is mainly for AD73360 slave card's hardware design,concrete dynamic testing methods and PC by detailed test.Through comparing the manual gives typical dynamic index,the slave card performance can satisfy the performance index of AD73360.
To meet the high-precision and high-reliability requirements of aerospace products,and achieve self-reliance in components and chip localization,as well as application adaptability verification,it is necessary to design a domestic DC/DC board-level comprehensive testing platform based on FPGA.In long-term thermal environmental adaptability board-level verification projects,to achieve real-time monitoring of the working status of DC/DC device application boards,a smart recognition algorithm based on Transformer is proposed.The deep learning model is trained using these features.The experiment results show that for this 6-state dataset,the recognition accuracy of the Transformer model is 99.2%,which has good classification and monitoring performance and has certain engineering application value.
The manufacturing of circuit boards plays an important role in the life cycle of electronic product production,and in each process of circuit board production,quality control of circuit boards is the most important link.The FCT system is specifically used to inspect the quality of circuit board soldering.This article introduces a design scheme for a circuit boss FCT system based on a three-layer structure and multi task queue.Firstly,the composition and explanation of the hardware equipment of the FCT system are introduced.Then,the overall architecture of the upper computer software of the FCT system,the division of functional modules,and the detailed functions of each module are introduced.The outstanding technical implementation methods of the upper computer software in this scheme are emphasized,including the three-layer hierarchical pattern,ORM (Object Relationship Mapping), and multi task queue.Finally,a program flowchart of the FCT system's operation is provided.Through the hardware and software design of the FCT system,the problem of quality inspection of circuit boards has been perfectly solved.
