With the evolution of advanced technology,the proportion of leakage power consumption in the total power consumption of integrated circuits continues to increase,which has gradually become one of the important factors restricting the reduction of circuit power consumption.Among the existing leakage power optimization methods,the method based on threshold voltage allocation has an exponential power optimization effect and has no influence on the layout and routing,so it is widely adopted.However,in commercial signoff tools,in order to maintain pseudolinear complexity,the global search made by the underlying algorithm is limited,which makes it difficult to obtain optimal results.In this paper,a joint optimization framework RL-LPO based on graph neural network and reinforcement learning is proposed to achieve efficient gate unit threshold voltage distribution.In RL-LPO,the timing and physical information of the graph neural network GraphSAGE encoding circuit are used to aggregate the target unit and its local neighborhood information.Using the Deep Deterministic Policy Gradient (DDPG) reinforcement learning algorithm,the threshold voltage allocation is carried out considering the leakage power consumption and timing variation under the guidance of the reward function.The gate unit threshold voltage distribution framework RL-LPO proposed in this paper is verified by IWLS2005 and Opencores reference circuits under the 28 nm process,and compared with commercial signoff tools,RL-LPO reduces the additional leakage power consumption by at least 2.1% and achieves at least 4.2 times acceleration without adding timing violations.

Sparse matrix solving is an important part of SPICE simulation.The operators currently used for solving are usually general-purpose floating-point calculation units.In order to solve the problem of double-precision floating-point speed in SPICE simulation,this article improves the addition/subtraction and multiplication units in general floating-point operators to enable faster solution speed in the context of SPICE simulation.The rounding parallel delay optimization algorithm and dual-path design scheme are used for the traditional addition and subtraction unit,and the critical path delay of the circuit is optimized by means of Shannon expansion and inexact leading zero compensation.For the traditional multiplication unit,the related delay is improved by changing the traditional compression topology layer structure and optimizing logic such as rounding and carry in the injection value algorithm.In the end,the double-precision floating-point solution achieved delays of 0.46 ns and 0.79 ns respectively under the TSMC 28 nm process.Compared with Synopsys' DW library unit,the delays are reduced by 33.4% and 7.1% respectively,and the area is reduced by 4.62% and 1.6% respectively.The experiment results show that the improved floating-point unit can effectively reduce the time of a single matrix solution step and accelerate the overall speed of transient simulation to a certain extent.

Integrated circuit technology is one of the core technologies of modern electronic engineering,which promotes the development of the entire science and technology industry.Starting from the whole industrial chain of integrated circuits,this paper briefly introduces the current situation of integrated circuit technology and industrial chain at home and abroad from four perspectives:device technology,manufacturing equipment,design tools and chip categories.In the future,with the advancement of technology and the growth of application demand,integrated circuits will continue to play a key role in promoting the sustainable development of the industry.It is hoped that this paper can inspire domestic counterparts,enrich the understanding of the current situation of the industry,and provide a certain reference value for the determination of the direction and goal of scientific research and application.

With the trend of digitization,intelligence,and networking sweeping the world,functional security and network security are increasingly intertwined and overlapping,evolving into endogenous security issues.The operating system is an important component of computer systems and the cornerstone of software architecture,and operating system level endogenous security is crucial.The dynamic heterogeneous redundant architecture based on mimetic defense is a key technology for achieving endogenous security in operating systems.However,it currently faces challenges such as single kernel operating systems not supporting endogenous security,lack of operating system level endogenous security solutions,and incomplete design of operating system level consensus mechanisms.This article analyzes and designs an embedded security architecture for operating systems,heterogeneous redundancy mechanisms,efficient communication,and consensus mechanisms,and proposes a multi kernel based embedded security technology solution for operating systems.

This paper explores the key technologies of an industrial robot operating system based on a mixed criticality system to address the technical challenges faced by robots in non-structured or semi-structured intelligent scenarios.With the rapid application of intelligent technologies in the field of robotics,the robot operating systems need to meet the requirements of strong real-time tasks for control systems and weak real-time tasks for intelligent applications.So a heterogeneous multi-core intelligent system is needed.The paper proposes an architecture design specifically tailored for robots,with the aim of enhancing the real-time performance,security,and intelligence level of robot operating systems.Furthermore,this paper provides insights into the future development trends of industrial robot operating systems and predicts the future evolution direction.

Aiming at the problem of occasional power loss that may occur in the complex environment of the bomb shipboard memory,a memory solution with power failure rewrite function is proposed to avoid the last stored data being overwritten by the new data after the memory recovers from the occasional power loss on the bomb arrows.The power down-surviving technique is implemented on the basis of write-while-erase,and cross-biplane programming is used to satisfy the data writing rate.The ground test bench simulates the data sent from the bomb system,and after a large number of tests,the results show that the design achieves the function of power failure renewal,and can achieve the stable storage of data,which verifies the reliability of the system.